With the continuous scaling of NAND flash memories, it becomes a greater challenge to provide guaranteed reliability at high performance and high endurance. One of the key tools for enabling NAND flash memory scaling is advanced controllers with high capabilities of digital signal processing and error correction. In this invention a building block of a digital signal processor (DSP) is suggested, for extending the NAND flash memory endurance and enabling higher performance. This building block controls fundamental parameters of the physical read/write of the flash array, which increase the number of reads that can be done from a programmed block before a refresh is required.